A receiver that can receive multiple transmission speed (bit-rate) signal and optimize its performance in dependence on the bit-rate is proposed (see Patent Document 1, for example). Such a receiver includes a bit-rate discrimination circuit that automatically discriminates the bit-rate of a received signal.
FIG. 1 shows a conventional bit-rate discrimination circuit described in the Patent Document 1. In FIG. 1, a reference numeral 10 denotes an input terminal; 11 denotes an output terminal; 12 denotes a delay circuit; 13 denotes a dual-input exclusive OR circuit; 14 denotes a mean value detector; 15 denotes a level decision circuit; and 16 denotes a reference voltage (Vref) input terminal. FIG. 2 shows the waveforms at various points in the bit-rate discrimination circuit shown in FIG. 1. In FIG. 2, the waveform A shows the waveform of an input signal; B shows the waveform of an output signal from the exclusive OR circuit 13; C shows the waveform of an output signal from the mean value detector 14; and D shows the waveform of an output signal from the level decision circuit 15. The point at which each waveform is measured is shown in FIG. 1.
The conventional bit-rate discrimination circuit includes the delay circuit 12 and the exclusive OR circuit 13 at the input stage, which generate and output a pulse at the rise and fall edge of the input signal A. The pulse width of the output pulse is determined by the delay time of the delay circuit 12. If the bit-rate of the input signal is high, the density of the pulse is high, and if the bit-rate of the input signal is low, the density is low. By averaging the density of the pulse using the mean value detector 14, the output voltage is high for a high bit-rate input signal, and low for low bit-rate input signal. The level decision circuit 15 compares the output voltage from the mean value detector 14 with the reference voltage (Vref), and output a control signal in dependence on the bit-rate. The conventional receiver described in the Patent Document 1 can receive signals of different bit-rates by adjusting the performance of a phase synchronization circuit using the above bit-rate discrimination circuit for feed-forward type bit-rate automatic control.
However, if used for a feed-back control type bit-rate automatic control, the conventional bit-rate discrimination circuit described above may fail to accurately discriminate the bit-rate. FIG. 3 is a block diagram showing an exemplary multi bit-rate receiver in which the above problem may occur. In FIG. 3, a reference numeral 1 denotes a photo detector; 2 denotes a power supply or an electrical ground; 3 denotes a single-end type amplifier; 4 denotes a buffer; 5 denotes a main amplifier; 6 denotes a bit-rate discrimination circuit; 7 denotes a variable feedback resistor; 8 denotes a preamplifier; and 9 denotes an output terminal.
An optical signal is converted into a current signal by the photo detector 1 such as a photo diode, and the current signal is input to the preamplifier 8. The preamplifier 8 includes a trans-impedance amplifier and a buffer 4, the trans-impedance amplifier consisting of a single-end type amplifier 3 and its feedback resistance 7. The trans-impedance amplifier can convert an input weak current signal into an amplified voltage signal. The buffer 4 is inserted for the purpose of improving the impedance matching between the trans-impedance amplifier and the main amplifier 5, and enabling single-balance conversion. The main amplifier 5 can limit the amplitude of a signal or automatically control gain thereby to amplify the output signal from the preamplifier 8 to a constant amplitude signal.
In general, receiver sensitivity is substantially determined by noise level of the preamplifier 8, and depends on the value of the variable feedback resistor 7 in the trans-impedance amplifier. If the value of the feedback resistor 7 is increased (hereinafter, referred to as low speed mode), the trans-impedance amplifier only can receive a low bit-rate signal because its band width becomes low. The trans-impedance gain is increased, and the minimum acceptable value of received power is improved because noise current is reduced. To the contrary, if the value of the variable feedback resistor 7 is low (hereinafter referred to as high speed mode), the trans-impedance amplifier can receive even a high bit-rate signal because its band width is increased. However, the trans-impedance gain is reduced, and the minimum acceptable value of received power is increased due to the increase in noise current. That is, there exists the optimal value of the variable feedback resistor 7 of the trans-impedance amplifier at which the bit-rate of the received optical signal is acceptable and at the same time the receiver sensitivity is as high as possible (the minimum acceptable value of received power is as low as possible). The multi bit-rate receiver shown in FIG. 3 uses feedback control type bit-rate automatic control that adjusts the value of the variable feedback resistor using the discrimination result of the bit-rate discrimination circuit 6 for the above optimization.
[Patent Document 1] JP2000-40960
However, the conventional multi bit-rate receiver described above may fail to accurately discriminate the bit-rate when the bit-rate is switched from low speed to high speed. In addition, even if a bit-rate discrimination circuit is used that can accurately discriminate the bit-rate even if the high frequency component of the signal is lost, the multi bit-rate receiver can not adjust itself to the change in the minimum acceptable value of received power due to the mode change of the preamplifier 8.